1. Field of Invention
The present invention relates to read-only-memory (ROM) devices, and more particularly, to a ROM array in which the coding step is performed after the metallization step.
2. Description of Related Art
In general, a ROM device is programmed in a code implantation step. The code implantation step, especially for a mask ROM device, is carried out prior to depositing a metal layer to cover the device. Therefore, some post-processing of the ROM device is necessary after the code implantation step. Since the post-processing processes, such as passivation formation, contact opening, metallization, packaging and testing take a lot of time, ROM devices cannot be produced soon after they are ordered. Thus, a coding after metallization technique has been developed to speed up the production of the ROM devices.
For example, in order to provide better conditions for coding after metallization and still follow the design rules, the layout configuration of a high-density mask ROM array, such as the flat-cell memory array, has to be arranged carefully. FIG. 1 (Prior Art) is a schematic diagram illustrating a conventional layout configuration of a ROM array, in which only one bank is shown. A plurality of bit lines 1 through 8 are made of diffusion regions. A plurality of word lines WL.sub.1 through WL.sub.n intersect the bit lines to form memory cells. For example, bit lines 6 and 7 construct the drain/source regions of cell M61, while word line WL1 is the gate. Therefore, spacings between bit lines become the channel regions of the memory cells. A number of metal lines 11 through 14 are formed between the bit lines for reading data stored in the memory cells. Thus, metal contacts with bit lines 1 through 8 are formed on opposite sides of the bank. In order to program the ROM array, impurities are implanted into the channel regions of specific memory cells, i.e., the spacings between the bit lines, in the code implantation step. Since metal lines 11 through 14 are usually formed after the code implantation step, the fact that the spacings between bit lines are covered by the metal lines does not affect the programming of the ROM array. However, if the code implantation step is to be carried out after the metallization step, the location of metal lines 11 through 14 must be modified.
A layout configuration for coding after metallization ROM array has been developed by modifying the structure of FIG. 1 (Prior Art), as illustrated in FIG. 2 (Prior Art). As is shown in FIG. 2 (Prior Art), metal lines 11 through 14 are formed over bit lines 2, 4, 6 and 8 to expose the substrate surface of the spacings between bit lines 1 through 8. Therefore, impurities can be easily implanted into the channel regions of the memory cells in the code implantation step. Referring to FIG. 3A, the coding of three memory cells of the ROM array is carried out by implanting ions into channel regions 21, 22 and 23 through an implanting mask as indicated by the dashed line. However, as the size of semiconductor devices decreases, the design rules become critical. Therefore, the implanting mask of FIG. 3A must be modified to the configuration of FIG. 3B. That is, the originally distinct implanting regions 21, 22 and 23 are merged into a single area indicated by the dashed line. Since bit lines 25, 26 and 27 are also diffusion regions, the broadening of the code implanting region will change the impurity concentrations in the bit lines and thus vary the conductivities.
The variation of the bit line conductivity will affect the data precision accessed over the metal lines. This effect will be explained. FIG. 4 (Prior Art) is a circuit diagram of the ROM array whose layout configuration is shown in FIG. 2 (Prior Art). In the ROM array, except for two memory cells M.sub.41 and M.sub.4n, all the memory cells are coded by implanting impurities into their channel regions. Therefore, all bit lines that are not covered by the metal lines also have impurities implanted into them. Since the sheet resistance of a diffusion region depends on the concentration of impurities therein, the code implantation will increase the sheet resistance of the bit lines which are implanted. In general, the ratio between original and implanted bit lines is about 120:180. That is, if the sheet resistance of the implanted bit lines is designated as R.sub.1 and that of the original bit lines is designated as R.sub.2, there is the relationship that R.sub.1 /R.sub.2 .apprxeq.3/2. Since the ratio is not unity, a problem of data precision may result.
The problem can be better understood through a description of the data reading paths to cells M.sub.41 and M.sub.4n which are illustrated in FIG. 5A (Prior Art) and FIG. 5B (Prior Art) respectively. Referring to FIG. 5A (Prior Art), the reading path to cell M.sub.41 includes a transistor BSO.sub.3, cell M.sub.41, bit line 4 and another transistor BSE.sub.2. Since bit line 4 is shielded by a metal line as shown in FIG. 2 (Prior Art), it has a sheet resistance of R.sub.2. Therefore, the resistance of bit line 4 can be represented as R.congruent.30R.sub.2 K, where K is the line width. As for cell M.sub.4n, the reading path includes transistor BSO.sub.3, bit line 5, cell M.sub.4n and transistor BSE.sub.2. As shown in FIG. 2 (Prior Art), bit line 5 is exposed and has been implanted with impurities after the coding step. Therefore, the resistance of bit line 5 is represented as R.congruent.30R.sub.1 K. Since R.sub.1 /R.sub.2 .congruent.3/2, sensing currents in bit lines 4 and 5 will have a ratio of about 2/3. It is difficult to design a sense amplifier to read sensing currents with such a wide variation, and thus it is impossible to obtain data with a high degree of precision.